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1. general description the sdio101 is a sd/sdio/mmc/ce-ata ho st controller with a standard 16-bit asynchronous memory interface. the device conforms to the sd host standard specification version 2.0 (see ref. 1 ). the sdio101 manages the physical layer of sd, sdio, mmc and ce-ata protocols and can be used together with sd host standard compatible driver software to add sd/sdio/mmc/ce-ata host functionality to a variety of microprocessor systems. the sdio101 supports both full-speed (< 25 mhz) and high-speed (< 52 mhz) data transmissions on the sd/sdio/mmc/ce-ata port . the sdio101 offers separate pins for sd/sdio/mmc/ce-ata port supply voltage, hos t interface supply voltage and core supply voltage. the sd/sdio/mmc/ce-ata port can operate at a wide voltage range (1.8 v to 3.6 v) which allows the device to interfac e to a large variety of sd, sdio, mmc or ce-ata devices. the sdio101 allows 1-bi t and 4-bit sd transactions and 8-bit mmc/ce-ata transactions. the 16-bit asynchronous memory interface can operate at a 2.5 v to 3.6 v voltage range. a built-in, 2 kb data buffer allows for a low interrupt latency time and efficient communication with the host processor at high data rates. the sdio101 provides a dma request line that can be connected to an ex ternal dma controller to off-load the host processor and increase overall system performance. an on-board pll allows a large range of sd/sdio/mmc/ce-ata clock speeds to be generated from a single externally available clock source. an additional fractional divider allows the sd clock speed to be fine-tuned with very fine granularity, which enables the user to achieve the maximum desired sd cl ock speed from the ex ternal clock source. the sdio101 offers 5 levels of power saving, including a ?hibernate mode? where the on-board oscillator, pll and dat a buffer memories are switch ed off, and a ?coma mode? in which supply power to most of the device is in ternally switched off. this allows the device to be used in very power-critical applications. 2. features 2.1 general ? provides 1 sd/sdio/mmc/ce- ata slot, operating in 1-bit, 4-bit and 8-bit (mmc/ce-ata) modes ? 2.5 v to 3.3 v host interface ? 1.8 v core supply voltage ? separate sd supply voltage pin. sd/sdio/mmc /ce-ata slot is able to operate at a wide voltage range (1.8 v to 3.3 v). sdio101 sd/sdio/mmc/ce-ata host controller rev. 03 ? 11 march 2010 product data sheet
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 2 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller ? compliant with sdio card specification version 2.00 (see ref. 2 ) ? compliant with sd host controller standard specification version 2.0 (see ref. 1 ) ? compliant with sd physical layer specification version 2.0 (see ref. 3 ) ? compliant with mmc specification version 3.31 and 4.2 (see ref. 4 ) ? supports ce-ata digital protocol revision 1.1 (see ref. 5 ) ? supports ce-ata digital protocol commands (cmd60/cmd61) ? dedicated sd card detection input pin (insertion/removal) ? dedicated sd card write protection input pin ? full speed (< 25 mhz) and high-speed (< 52 mhz) sd data transmissions ? supports interrupt and slave-dma transfer operation ? built-in 2 kb double data buffer (with 1 kb maximum block size) for efficient communication with host processor ? supports sdio features multi-block, suspend/resume, read wait and wake-up control ? up to 400 mbit/s read and write data transfer rates at 50 mhz using mmc 8 data lines ? up to 208 mbit/s read and write data tran sfer rates at 52 mhz using sd 4 data lines ? on-board crystal oscillator and pll ? 5 levels of power saving, including a ?hib ernate mode? where oscillator, pll and memories are switched off, and a ?coma mo de? that internally switches off supply power to most of the chip ? additional on-board fractional clock divider for fine-grained sd clock speed control ? cyclic redundancy check ( crc) for command and data ? programmable pull-up resistor on sd cmd and sd datn lines ? programmable drive strength for sdclk out put to optimize sd/sdio/mmc/ce-ata clock speed 2.2 host processor interface ? supports 16-bit asynchronous memory interface ? separate host interface power supply pin, able to operate on 2.5 v to 3.3 v ? programmable open collector or push-pull mode for int interrupt pin output 3. ordering information [1] package approved for manufacture, but not currently available for standard ordering. contact interface.support.nxp.com . table 1. ordering information type number package name description version SDIO101IET [1] tfbga64 plastic thin fine-pit ch ball grid array package; 64 balls; body 4 4 0.8 mm sot969-1 sdio101ihr hxqfn60u plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; utlp based; body 5 5 0.5 mm sot1133-1
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 3 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 4. block diagram fig 1. block diagram of sdio101 sdio101 002aae475 16-bit asynchronous memory interface cs a[7:1] d[15:0] re we be[1:0] int dreq power management data buffer v dd(io) v dd v dd(sd) sd/sdio/ mmc/ce-ata host interface reset oscillator pll additional clock control x2_clk x1_clk sdclk dat[7:0] cmd sdcd sdwp pow[1:0] a8 v dda
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 4 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 5. pinning information 5.1 pinning fig 2. pin configuration for tfbga64 (see table 1 , table note [1] ) transparent top view. fig 3. ball mapping for tfbga64 (see table 1 , table note [1] ) 002aad06 5 SDIO101IET transparent top view ball a1 index area 18 7 6 5 4 3 2 b c d e f g h a a5 1 a 002aad06 4 a6 b re c gnd d int e dreq f x1_clk g v dd(sd) h a3 2 a4 a7 a8 be1 v dda x2_clk gnd d15 3 a1 a2 v dd(io) be0 gnd sdclk cmd d13 4 d14 d11 d12 v dd dat0 dat1 dat2 d10 5 d9 d7 gnd dat3 v dd(sd) dat4 gnd v dd(io) 6 gnd d3 gnd reset dat7 dat6 dat5 d6 7 d5 d1 d8 cs pow0 v dd(sd) sdcd d4 8 d2 d0 we v dd(io) pow1 gnd sdwp
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 5 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller fig 4. pin configuration for hxqfn60u sdio101ihr 002aaf24 3 transparent top view d1 d5 b20 b19 b18 b17 b16 b6 b7 b8 b9 b10 d8 d6 d7 a24 a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b15 b14 b13 b12 b11 a7 a8 d2 a23 a22 a21 a20 a19 a18 a17 d3 a32 a31 a30 a29 a28 a27 a26 a25 a9 a10 a11 a12 a13 a14 a15 a16 d4 terminal a1 index area
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 6 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller fig 5. terminal mapping for hxqfn60u sdio101ihr 002aaf244 transparent top view d1 d5 b20 b19 b18 b17 b16 b6 b7 b8 b9 b10 d8 d6 d7 a24 a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b15 b14 b13 b12 b11 a7 a8 d2 a23 a22 a21 a20 a19 a18 a17 d3 a32 a31 a30 a29 a28 a27 a26 a25 a9 a10 a11 a12 a13 a14 a15 a16 d4 terminal a1 index area x1_clk v dd v dda dreq be1 v dd(io) re a6 a5 a7 a8 be0 int gnd sdclk dat0 dat1 dat3 gnd dat5 dat6 sdcd x2_clk v dd(sd) v dd(sd) cmd dat2 dat4 dat7 v dd(sd) sdwp pow1 pow0 reset cs v dd(io) gnd we d8 d4 d2 d1 d3 d0 d5 gnd v dd(io) d6 d7 d9 d10 d11 d12 d13 d14 d15 a1 a2 a3 a4
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 7 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 5.2 pin description 5.2.1 pin description by function following are the signal descriptions on the sdio101 interfaces. pins are organized by function. table 2. pin description by function b = bidirectional; i = input; o = output; n.c. = not connected. symbol pin type description tfbga64 [1] hxqfn60u sd/sdio/mmc/ce-ata interface signals sdclk g3 a9 o sd clock output. this output clock is driven by the host controller during read and write transactions. cmd h3 b6 b sd command line. this bidirectional signal is used to transfer commands and responses between the host and the card. dat0 f4 a10 b sd data bit 0. dat1 g4 a11 b sd data bit 1. dat2 h4 b7 b sd data bit 2. dat3 e5 a12 b sd data bit 3. dat4 g5 b9 b sd data bit 4. dat5 h6 a14 b sd data bit 5. dat6 g6 a15 b sd data bit 6. dat7 f6 b10 b sd data bit 7. sdcd h7 a16 i sd card detect (active low). this pin can be used to detect insertion and removal of sd/sdio/mmc cards. sdwp h8 d3 i sd write protect (active low). this pin can be used to detect if the inserted sd/sdio/mmc ca rd is write protected. system interface signals x1_clk g1 a8 i clock input. must be connected to the syst em clock which is used to generate the host bus interface (see section 6.4.3.1 ). x2_clk g2 d2 o clock output. reset e6 a18 i asynchronous reset (active high). this active high input pin unconditionally resets the entire device. card power supply control interface signals pow[1:0] f8, f7 b11, a17 o sd power supply control bits. these bits can be used to control the voltage of an external power su pply for the sd/sdio/mmc/ce-ata device. see ta b l e 4 for details.
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 8 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller [1] refer to table 1 , table note [1] . host interface control signals cs e7 a19 i chip select (active low). a[7:1] c2, b1, a1, b2, a2, c3, b3 b1, a1, d1, d5, a32, b20, a31 i address lines. can be used to address the 256 bytes of the standard host register space. a8 d2 b2 i address 8. when accessing sdio101 transmit or receive buffer under dma control, this pin must be high. this pin must be low when accessing other registers or when accessing transmit or receive buffer under interrupt control. d[15:0] a3, b4, a4, d4, c4, a5, b5, d7, c5, a7, b7, a8, c6, b8, c7, c8 a30, b19, a29, b18, a28, a27, b17, a21, a26, d4, d8, a24, b15, a23, a22, b14 b data lines. used to transfer data between host controller and the processor. re c1 a2 i read enable (active low). initiates a read transaction when active. we d8 b13 i write enable (active low). initiates a write transaction when active. be[1:0] e2, e3 a5, b3 i byte write enables (active low). when be[0] is active, the least significant byte on the data bus can be written. when be[1] is active, the most significant byte on the data bus can be written. int e1 b4 o interrupt reques t (active low). can be configured as push/pull or open-collector output. dreq f1 a6 o dma request. power interface signals v dd e4 a4 - core power supply pin, 1.8 v. v dda f2 a7 - analog power supply, 1.8 v. v dd(sd) f5, g7, h1 d6, b8, d7 - sd power supply pins, 1.8 v to 3.3 v. v dd(io) a6, d3, e8 b12, b16, a3 - host interface power supply pins, 2.5 v to 3.3 v. gnd b6, d1, d5, d6, f3, g8, h2, h5 b5, a13, a20, a25 - ground. table 2. pin description by function ?continued b = bidirectional; i = input; o = output; n.c. = not connected. symbol pin type description tfbga64 [1] hxqfn60u
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 9 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 6. functional description the sdio101 offers the sd standard host register set as defined in the sd host standard specification version 2.0 (see ref. 1 ), through which the host driver software can configure the host controller and initiate transactions to and from an sd/sdio/mmc/ce-ata target. on top of the st andard host registers, 4 extra registers are available in the host controller register space, which can be used to control the additional features in th e sdio101. these features are described in detail in section 6.4 . section 6.2 gives an overview of the sdio101 register set. 6.1 dma mode the sdio101 supports slave dma where the transferring of data between the host and the sdio101 is under the control of the host?s dma controller. in this mode, the software can program dma burst size (n umber of 16-bit words per dma cycle) as well as the delay between back-to-back dma requests from sdio101. in dma mode, buffer data port 0 (0x20) and buffer data port 1 (0x22) are mapped differently than in interrupt mode?address line a8 must be at logic 1 when buffer data ports are being accessed while the rest of the address lines are ignored by the sdio101. once the dma operation starts, all the access es to the sdio101 with a8 set to logic 1 will be considered as buffer data ports access. to access other sdio101 internal registers, address a8 must be set to logic 0. the total number of dma accesses to the buffer data ports must be an even number. the first access from the host will be to buffer data port 0, and the second access will be to buffer data port 1. the sdio101 will automatically alternate between buffer data port 0 and buffer data port 1 on each access by the host. this scheme allows the sdio101 buffer data ports to look like a continuous block of memory or fifo to the dma controller. there are two registers that must be pr ogrammed for the sdio101 to support dma operation: ? miscellaneous register (0xf8) bit 1 (enable slave dma) must be set to logic 1. ? dma burst size and dma inter delay (back-to-back dreqs) must be programmed through dma register (0xf4). dma register bit [8:0] programs the dma burst size (the number of 16-bit words to be transferred between the dma controller and the sdio101), and dma register bit [15:9] programs the delay time between two back-to-back dma requests from sdio101 (the inter delay va lue in bit [15:9] represents the number of sd clocks). 6.1.1 dma read when the receive buffer is empty, dreq is at low state. once the receive buffer has at least the number of 16-bit words equal to the programmed dma burst size (dma register [8:0]) dreq goes high. the dma cont roller then can perform a block read of the receive buffer with the block size equal to the programmed dma burst size in the dma register. the dreq will go low once a block of data has been read from th e sdio101?s receive buffer, and dreq will remain lo w for a period defined by dm a register bit [15:9]. the dreq signal will go high again if the receive bu ffer still holds at least the burst size of 16-bit word data.
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 10 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 6.1.2 dma write when the transmit buffer is empty, dreq is at high state. the dma controller then can perform a block write to the receive buffer with the block size equal to the programmed dma burst size programmed in dma register [9:0]. the dreq will go low once a block of data has been written to the sdio101?s transmit buffer, and dreq will remain lo w for a period defined by dm a register bit [15:9]. the dreq signal will go high again if the transmit buffer still has space to hold at least the burst size of 16-bit word data. 6.2 standard host register overview [1] this register is not part of the standard host register set. table 3. sd host controller register map offset bits 15:8 bits 7:0 offset bits 15:8 bits 7:0 0x02 system address (high) 0x00 system address (low) 0x06 block count 0x04 block size 0x0a argument1 0x08 argument0 0x0e command 0x0c transfer mode 0x12 response1 0x10 response0 0x16 response3 0x14 response2 0x1a response5 0x18 response4 0x1e response7 0x1c response6 0x22 buffer data port1 0x20 buffer data port 0 0x26 present state 0x24 present state 0x2a wake-up control block gap control 0x28 power control host control 0x2e software reset time-out control 0x2c clock control 0x32 error interrupt status 0x30 normal interrupt status 0x36 error interrupt status enable 0x34 normal interrupt status enable 0x3a error interrupt signal enable 0x38 normal interrupt signal enable 0x3e reserved 0x3c auto cmd12 error status 0x42 capabilities 0x40 capabilities 0x46 capabilities (reserved) 0x44 capabilities (reserved) 0x4a maximum current capabilities 0x48 maximum current capabilities 0x4e maximum current capabilities (reserved) 0x4c maximum current capabilities (reserved) 0x52 (reserved) 0x50 [1] io-cell configuration -- -- 0xf6 [1] secondary clock control 0xf4 [1] dma register 0xfa [1] pll 0xf8 [1] miscellaneous 0xfe host controller versio n 0xfc slot interrupt status
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 11 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 6.3 standard host regi ster set description the sdio101 registers that are part of the standard host register set are described in detail in ref. 1 . in this paragraph, we will only descri be the specific impl ementation of the standard register set in the sdio101 that are different from ref. 1 . 6.3.1 system address register (offset 0x00) since master-dma functionality is not implemented, all bits in this register will always read zero. writes to this register will be ignored. 6.3.2 block size register (offset 0x04) data written to bits r[14:1 2] will be ignored. the maximu m block size that can be programmed is 1 kb. any block size higher than that will default to 1 kb. 6.3.3 transfer mode register (offset 0x0c) since master-dma functionality is not implemented, bit r[00 ] will always read zero. writes to this bit will be ignored. 6.3.4 present state register (offset 0x24) the sdio101 supports multiple buffers, that is, the available data buffer space (2 kb) is larger than the maximum block size (1 kb). the buffer write enable bit r[10] indicates that there is room to write at least one more single block length (as specified in the block size register) in the data buffer even thou gh previously-written blocks might still be present. similarly, the buffer read enable r[11] bit indicates that there is at least one single block length (as specified in the block size register) available in the data buffer. 6.3.5 host control register (offset 0x28) a separate led control pin sdld is not supported in the sdio10 1. if desired, the user can use a gpio pin on the host processor to im plement this functiona lity. bit r[00] in the host control register will a lways read zero, and writing to it will have no effect. 6.3.6 power control register (offset 0x29) bits r[03:00] control the pow[1:0] pins of t he sdio101, which can be used to control an external power supply that powers the sd/sdio/mmc/ce-ata device. two power modes are supported: ?normal? and ?low power?. it is up to the user to decide what voltage to associate with normal and low-power modes, but a typical implementation is 3.3 v for normal and 1.8 v for low power mode. ta b l e 4 shows the relation between the power control register and the pow[1:0] pins. table 4. relation between the power co ntrol register and the pow[1:0] pins power control register r[03:00] pow[1:0] description xxx0b 00b sd power off 1011b 01b sd low power (1.8 v) on 1101b 10b sd normal power (3.3 v) on 1111b 10b sd normal power (3.3 v) on
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 12 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 6.3.7 capabilities register (offset 0x40) the sdio101 capabilities regist er contents are shown in ta b l e 5 . 6.4 additional register set description the additional registers are not part of the sd host standard specification version 2.0 (see ref. 1 ). these registers do not have to be initialized, so standard host driver software does not have to be aware of them. 6.4.1 io configuration register (offset 0x50) the io configuration register offers three bits to set the drive strength of the io cell used for driving the sdclk pin. this way the user can adjust sdclk rise/fall times according to their system performance requ irements. typically, drive stre ngth should be set to low when the sd slot is operating on normal (2 .7 v to 3.3 v) voltage, and to high when the sd slot is operating on low voltage (1.8 v). also, a bit is offered to disable the default pull-up resistors on the sd cmd and sd datn lines, in case they are not required and the possible leakage current through these resistors is undesired. table 5. contents of the capabilities register (offset 0x40) location attribute default description 63:27 reserved 00h reserved 26 r 1b low voltage (1.8 v) supported 25 r 0b 3.0 v not supported (defaults to normal voltage) 24 r 1b normal voltage (3.3 v) supported 23 r 1b suspend/resume supported 22 r 0b master dma not supported 21 r 1b high speed sd (> 25 mhz) supported 20:18 reserved 00h reserved 17:16 r 01b 1 kb maximum block length 15:14 reserved 00h reserved 13:08 r 00h get info through other method ( ref. 1 ) 07 r 1b time-out clock unit in mhz 06 reserved 0b reserved 05:00 r 00h get info through other method ( ref. 1 ) fig 6. io configuration register d00 002aac757 d03 d02 d01 sdclk drive strength sd pu enable d06 d05 d04 d09 d08 d07 d12 d11 d10 d15 d14 d13 reserved
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 13 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 6.4.2 dma register (offset 0xf4) the dma register is located in the common register area. this register controls the dreq output. the dreq low and high ti mes are programmed with dma inter delay and dma burst size. remark: refer to section 6.1 for more detailed dma description. table 6. contents of the io conf iguration register (offset 0x52) location attribute default description 15:04 reserved 0h reserved 03:01 r/w 3h sdclk drive strength select. these bits can be used to program the drive strength of the sdclk io cell. ta b l e 7 shows the possible values. 00 r/w 0b sd line pull-up. if set to b1, the internal pull-up resistors on the sd cmd and sd datn lines are switched off. table 7. sdclk drive strength programming io configuration register r[03:01] sdclk drive strength 000b low (sd operating on 2.7 v to 3.6 v) 0001b reserved 010b reserved 011b reserved 100b high (sd operating on 1.8 v) 101b reserved 110b reserved 111b reserved fig 7. dma register table 8. dreq control programming location attribute default description 15:09 r/w 0h dreq delay period (dreq low time) low time = value sd clock cycle time 08:01 r/w 0h dma burst size (dreq high time) d00 002aad32 1 d03 d02 d01 dma burst size d06 d05 d04 d09 d08 d07 d12 d11 d10 d15 d14 d13 dreq inter delay
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 14 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 6.4.3 secondary clock control register (offset 0xf6) the secondary clock control register is located in the common register area. this register gives the user more control over the clock generation. an additional fractional divider is offered to program the sdclk base frequency with higher granularity, allowing the design to use an existing (a vailable) clock rather than an external crystal or oscillator. figure 8 shows the architecture of the secondary clock control. the sdclk base frequency can be calculated with equation 1 : (1) where ?divisor? is the standard divisor as programmed in the clock control register; n is the integer divisor as programmed in the secondary clock control register r[07:00]; m is the fractional divisor as programmed in the secondary clock control register r[11:08]. figure 9 and ta b l e 9 below show the register bits of the secondary clock control register. (1) divisor is set by the clock control register (0x2c). fig 8. secondary clock control architecture 002aac758 secondary clock control register bypass pll register f pll f osc pll f osc (b + 1) bp crystal oscillator x1_clk x2_clk fractional divider f pll n + m 16 n m sd slot 1 clock control register f sdclk(base) divisor divider f/divisor (1) sd controller f fig 9. secondary clock control register table 9. contents of the secondary cl ock control register (offset 0xf6) location attribute default description 15:12 reserved 00h reserved 11:08 r/w 00h fractional divisor value m 07:00 r/w 01h integer divisor value n f sdclk base () f pll divisor n m 16 ----- - + ?? ?? ---------------------------------------- - = d00 002aac75 9 d03 d02 d01 integer divisor n d06 d05 d04 d09 d08 d07 d12 d11 d10 d15 d14 d13 reserved fractional divisor m
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 15 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 6.4.3.1 sdio101 x1_clk input the sdio101 sd bus must be synchronized to the host processor read and write operations. the device is designed such that the x1_clk input must be connected to the processor?s system clock ( figure 10 ). or alternatively, the x1_clk can be connected to the processor crystal clock output ( figure 11 ). in either case, the sdio101 internal pll can be used to boost up the x1_clk input then divided down to the desired sdio clock by using the internal divider in combination with the built-in fractional divider. figure 12 details a typical scenario where the host processor uses a 13 mhz crystal as its clock source, and the same clock is used by the sdio101 to operate the sd clock as close to 50 mhz as possible. with its input clock supplies by the processo r crystal output, the sdio101 internal pll (0xfa) is used to boost the input frequency to 104 mhz, the standard clock control register (0x2c) and the fractional divider (0xf6) registers are then used to divide the 104 mhz to about 48.9 mhz to be used as sd clock. fig 10. x1_clk connected to processor?s system clock fig 11. x1_clk connected to processor crystal clock output fig 12. host processor using 13 mhz crystal as clock source 002aad50 5 programmable oscillator divider x1_clk clock in host cpu clock clock out sdio101 002aad50 6 x1_clk host sdio101 x1 x2 002aad50 7 x1_clk host sdio101 x1 x2 13 mhz
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 16 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller pll register (0xfa) settings: bit 15 = 0b bit 14 = 0b bit [13:7] = 0000000b bit [6:5] = 01b bit [4:0] = 00111b; b = 7 fractional divider (0xf6) settings: bit [15:12] = 0000b; reserved bit bit [11:8] = 0010b; m = 1 bit [7:0] = 00000001b; n = 1 clock control register (0x2c) settings: bit [15:0] = 103h = (13 mhz 8) / (2 (1 + 2 / 16)) = 48.9 mhz 6.4.4 miscellaneous register (offset 0xf8) the miscellaneous register is located in the common register area. this register can be programmed to put th e device in the ?coma mode? or ?hibernate mode?, extra-low power-down modes on top of the standby mo de programmable through bit r[00] in the clock control register. also, a bit is offered to disable the dreq dma request line on the host interface. lastly, a bit is offered to switch between open-drain and push-pull mode for the int interrupt output pin. figure 13 and ta b l e 1 0 below show the register bits of the miscellaneous register. f sdclk base () f pll divisor n m 16 ----- - + ?? ?? ------------------------------------------ - = fig 13. miscellaneous register d00 002aac761 d03 d02 d01 d06 d05 d04 d09 d08 d07 d12 d11 d10 d15 d14 d13 reserved slave dma enable coma mode int mode hibernate mode
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 17 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 6.4.5 pll register (offset 0xfa) the pll register is located in the common regi ster area. this register provides control over the phase-locked loop, which is used in the sdio101 to generate an sd base clock frequency from the crystal osc illator or external cl ock source. th e default values of this register are such that the pl l multiplies the incomi ng frequency from the crystal oscillator by 5. this means that, if the pll register is not programmed, the frequency generated by the crystal oscillator or extern al clock source shou ld be 10.4 mhz in or der to generate the 52 mhz maximum sdclk speed. for the sd ba se clock frequency generated by the pll from the crystal oscillator frequency it holds (2) where b is the feedback divider value as programmed in r[04:00] of the pll register. the user should determine the desired f pll , choose the required value b for the feedback divider based on the available clock source f osc , and then choose a value for post divider p (as programmed in r[06:05]) such that the following condition gets satisfied: (3) the post divider setting decided by the value of p does not affect the frequency value (in mhz) of the f pll . the only advantage of this post divi der is in adjusting the duty cycle of the resulting f pll clock. the greater the value of p, th e closer the duty cycle will be to 50 % (provided the condition mentioned in equation 3 is not violated, for a guaranteed behavior). the pll register also provides the possibility to bypass the pll post divider, effectively setting a value of 1 for p. also, th e user can bypass the entire pll. figure 14 and ta b l e 11 show the register bits of the pll register. table 10. contents of the miscellaneous register (offset 0xf8) location attribute default description 15:03 reserved 00h reserved 02 r/w 0b int mode select. when set to 0b, the int interrupt output pin will be open-drain mode. an external 10 k pull-up resistor is required in this case. w hen set to 1b, the int interrupt output pin will be in push-pull mode. 01 r/w 1b slave dma enable. if programmed to 1b, the dreq signal will be functional. if programmed to 0b, the dreq signal will be fixed to zero. 00 r/w 0b coma mode. if programmed to 1b, power will internally be switched off to most of the device, resulting in a very low coma mode current. all state in the device will be lost, and no registers can be read or written, with the exception of the ?software reset for all? bit in the software reset register. setting this bit will re-instate power to the entire chip, and reset the sdio101. a hard-reset on the reset pin will also bring the device back out of coma mode. f pll b1 + () f = clk 156 mhz 2 p 1 + () f pll 320 mhz < <
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 18 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 6.4.6 host controller version register (offset 0xfe) the sdio101 host controller version is shown in table 12 . fig 14. pll register table 11. contents of the pll register (offset 0xfa) location attribute default description 15 r/w 0b pll bypass. if this bit is 1b, the pll is bypassed. the sdclk base frequency is then equal to the frequency provided by the oscillator, either generated by a crystal or generated by an external clock. if this bit is 0b, the pll is not bypassed. 14 r/w 0b pll direct. if this bit is 1b, the post divider of the pll is bypassed, effectively setting the post divider value p to 1b. in this mode, the duty cycle out of the pll can be unequal to 50 %. if set to 0b, the post divider p is used, and its value is determined by r[06:05] of the pll register. 13:07 reserved 00h reserved 06:05 r/w 01h pll post divider p 04:00 r/w 05h pll feedback divider b d00 002aac76 0 d03 d02 d01 post divider p d06 d05 d04 d09 d08 d07 d12 d11 d10 d15 d14 d13 reserved pll bypass pll direct feedback divider b table 12. contents of the host controller version register (offset 0xfe) location attribute default description 15:08 r 01h sdio101 version 1.0 07:00 reserved 00h reserved
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 19 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 6.5 power-saving modes the sdio101 provides 5 power-saving modes that can be used in different situations to minimize the power consumption of the device. ta b l e 1 3 below describes these modes and their associated register bits that can be programmed to enable them. idle, low power and standby modes can be used if card interrupts shoul d still be serviced. the hibernate mode will switch off the power to the sd de vice and the coma mode switches off most of the host controller, therefor e, card interrupts will not be generated. ta b l e 1 3 shows the 5 power-saving modes. 7. application design-in information table 13. sdio101 power saving modes mode associated register bits description idle mode clock control register r[02] sd card clock stopped; oscillator and pll is active. low power mode power control register r[00] sd card power switched off. standby mode clock control register r[00] when the clock control register r[00] is set to b0, the sdio101 internal clock is stopped, the pll is in power-down mode, the oscillator is active and all regist er states are maintained. the device will still respond to card interrupts. when waking up from standby mode, after writing a b1 in the clock control register r[00], the data buffer fifo pointers will reset to empty. coma mode miscellaneous register r[00] when the miscellaneous register r[00] is set to b1, the sdio101 internal power is switched off. all device pins are 3-stated, and only a write to the ?sof tware reset for all? bit in the software reset register or a hard reset on the reset pin will wake up the device. all device states, including data buffer contents, are lost. card insertion and removal detection through the sdcd pin is disabled. hibernate mode miscellaneous register r[03] the oscillator, pll and supply to the buffer memory will be switched off. all states are maintained, but data buffer contents are lost. upon wake-up, the data buffer fifo pointers will reset to empty. card insertion and removal detection through the sdcd pin is disabled. fig 15. typical application: host and card interface 002aad06 3 sdio core host interface card interface v dd(io) = 3.3 v v dd = 1.8 v v dd(sd) = 1.8 v or 3.3 v sdio controller sd power supply 3.3 v/1.8 v pow0 pow1 card
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 20 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 8. basic architecture the sdio101 provides sd/sdio/mmc/ce-ata fu nctionality to a microprocessor system as illustrated in figure 16 . a standard sd/sdio/mmc/ce-ata driver running on the host processor will be able to access the standard host register set in the sdio101 through the 16-bit memory interface, and initiate transactions to and from the sd card. an external sd power supply (controlled by the sdio101) can be used to supply the sd card. fig 16. sdio101 used in a microprocessor application 002aac85 4 sdio101 cs a[7:1] d[15:0] re we be[1:0] int dreq microprocessor dma controller pow[1:0] sdclk cmd dat[7:0] sd power supply v dd v ss card x1_clk a8 sdcd sdwp
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 21 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 9. limiting values 10. recommended operating conditions [1] if the pll is not bypassed, the minimum input frequency is 10 mhz. table 14. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd(io) input/output supply voltage host interface; in 2.5 v to 3.3 v range ? 0.3 +4.6 v v dd(sd) sd supply voltage sd interface in 1.8 v range ? 0.3 +1.95 v in 3.3 v range ? 0.3 +3.6 v v dd supply voltage core; 1.8 v range ? 0.3 +2.4 v v i input voltage on any input pin 1.8 v interface v ss ? 0.3 v dd +0.6 v 3.3 v interface ? 0.3 +3.6 v t amb ambient temperature operating ? 40 +85 c t stg storage temperature ? 65 +150 c v esd electrostatic discharge voltage sd/mmc/sdio interface; human body model ? 4+4kv table 15. operating conditions symbol parameter conditions min typ max unit v dd supply voltage core 1.65 1.8 1.95 v v dd(io) input/output supply voltage host interface 2.25 3.3 3.6 v v dd(sd) sd supply voltage sd interface 1.65 3.3 3.6 v f clk(ext) external clock frequency [1] 1- 52mhz i dd(av) average supply current f = 13 mhz; sdclk = 25 mhz -6-ma i dd supply current standby mode - 460 - a hibernate mode - 69 - a coma mode - 5 - a t oper operating temperature ? 40 +25 +85 c
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 22 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 11. static characteristics [1] x1_clk = 3.3 v only. [2] i dd is the supply on v dd and v dda . [3] i dd(io) current might be higher or lower depending on the activity of th e 16-bit data bus. the numbers specified in the data sheet are measured with no activity on the hos t controller bus. the data bus, address bus and control signals are pulled high. table 16. static characteristics symbol parameter conditions v dd(io) =2.5v v dd(io) =3.3v unit min max min max v il(clk) clock low-level input voltage x1_clk [1] ? 0.3 +0.6 ? 0.3 +0.6 v v ih(clk) clock high-level input voltage x1_clk [1] 2.4 v dd 2.4 v dd v v il low-level input voltage ? 0.3 +0.65 ? 0.3 +0.8 v v ih high-level input voltage 1.6 v dd 2.1 v dd v v ol low-level output voltage i ol = 2 ma - 0.4 - 0.4 v v oh high-level output voltage i oh = ? 800 a 1.4 - 2.1 - v i lil low-level input leakage current - 10 - 10 a i lih high-level input leakage current - 10 - 10 a i l(clk) clock leakage current x1_clk - 30 - 30 a c i input capacitance - 5 - 5 pf dynamic average supply current (v dd(sd) = 3.3 v) i dd(av) average supply current 25 mhz [2] -7-7ma 52 mhz [2] -9-9ma i dd(io) input/output supply current 25 mhz [3] - 1.3 - 1.5 ma 52 mhz [3] - 1.3 - 1.5 ma i dd(sd) sd supply current 25 mhz - 1.5 - 1.5 ma 52 mhz - 2.3 - 2.3 ma hibernate mode supply current (v dd(sd) = 3.3 v) i dd supply current [2] -130-130 a i dd(io) input/output supply current 25 mhz [3] -20-20 a i dd(sd) sd supply current - 1.5 - 1.5 a standby mode supply current (v dd(sd) =3.3v) i dd supply current [2] -4-4ma i dd(io) input/output supply current [3] -20-20 a i dd(sd) sd supply current - 1.5 - 1.5 a coma mode supply current (v dd(sd) =3.3v) i dd supply current [2] - 0.6 - 0.6 a i dd(io) input/output supply current [3] -20-20 a i dd(sd) sd supply current - 0.5 - 0.5 a
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 23 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 12. dynamic characteristics table 17. dynamic characteristics for 16-bit host bus interface symbol parameter conditions v dd(io) =2.5v v dd(io) =3.3v unit min max min max t wl(x1_clk) x1_clk pulse width low 9 - 9 - ns t wh(x1_clk) x1_clk pulse width high 9 - 9 - ns f x1_clk frequency on pin x1_clk - 52 - 52 mhz t su(a) address set-up time 5 - 5 - ns t h(a) address hold time 10 - 5 - ns t h(we-cs) hold time from we to cs 0-0-ns t d(csl-wel) delay time from cs low to we low 0 - 0 - ns t w(we) we pulse width 10 - 20 - ns t d(we) we delay time 10 - 20 - ns t su(d-weh) set-up time from data input to we high 5-5-ns t h(weh-d) data input hold time after we high 5-5-ns t su(ben) set-up time on pin ben 5-5-ns t h(ben) hold time on pin ben 5-5-ns t h(re-cs) hold time from re to cs 0-0 ns t d(cs-re) delay time from cs to re 0-0 ns t w(re) re pulse width 25 - 20 ns t d(re) re delay time 10 - 10 ns t d(re-q) delay time from re to data output 25 pf load - 20 - 25 ns t dis(re-qz) disable time from re to high-impedance data output 25 pf load - 20 - 15 ns t w(reset) pulse width on pin reset 10 - 5 - ns t d(buf_full-intl) delay time from buffer full to int low receive buffer (receive) - 4xtal1 - 4xtal1 ns t d(int_clr-inth) delay time from interrupt clear to int high receive buffer (read) - 300 - 300 ns t d(buf_emp-intl) delay time from buffer empty to int low transmit buffer (transmit) - 4xtal2 - 4xtal2 ns t d(int_clr-inth) delay time from interrupt clear to int high transmit buffer (write) - 80 - 80 ns t su(a8) address 8 set-up time 5 - 5 - ns t su(a8-cs) set-up time from address 8 to cs 5-5-ns t d(sdclk-dreqh) delay time from sdclk to dreq high - 20 - 15 ns t d(csh-dreql)w write delay time from cs high to dreq low - 20 - 15 ns t d(csh-dreql)r read delay time from cs high to dreq low - 20 - 15 ns
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 24 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller table 18. dynamic characteristics for mmc/sd/sdio bus interface v dd(sd) = 2.7 v to 3.3 v. symbol parameter conditions 25 mhz 52 mhz unit min max min max clock t wl clock low time 10 pf max. 12 - 8 - ns t wh clock high time 10 pf max. 12 - 8 - ns t w(clk) clock pulse width 10 pf max. 40 - 18 - ns t tlh clock rise time 10 pf max. - 10 - 3 ns t thl clock fall time 10 pf max. - 10 - 3 ns input cmd, datn t isu input set-up time 10 pf max. 5 - 6 - ns t ih input hold time 10 pf max. 5 - 2 - ns output cmd, datn t odly output delay time during data transfer mode; 40 pf max. 0 14 - 14 ns t oh output hold time 2.5 - 2.5 - ns table 19. dynamic characteristics for mmc/sd/sdio bus interface v dd(sd) = 1.70 v to 1.95 v. symbol parameter conditions 25 mhz 52 mhz unit min max min max clock t wl clock low time 10 pf max. 12 - 8 - ns t wh clock high time 10 pf max. 12 - 8 - ns t w(clk) clock pulse width 10 pf max. 40 - 18 - ns t tlh clock rise time 10 pf max. - 10 - 3 ns t thl clock fall time 10 pf max. - 10 - 3 ns input cmd, datn t isu input set-up time 10 pf max. 5 - 6 - ns t ih input hold time 10 pf max. 5 - 2 - ns output cmd, datn t odly output delay time during data transfer mode; 40 pf max. 0 14 - 14 ns t oh output hold time 2.5 - 2.5 - ns
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 25 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 12.1 timing diagrams fig 17. 8-bit write a[7:1] cs we be0 to be1 d[15:0] t su(a) 002aad30 1 t su(a) t su(ben) t h(a) t h(we-cs) t d(we) t h(ben) 10b t su(d-weh) t h(weh-d) d[7:0] 01b d[15:8] t w(we) fig 18. 16-bit write a[7:1] cs we be0 to be1 d[15:0] t su(a) 002aad30 2 t su(a) t su(ben) t h(a) t h(we-cs) t d(we) t h(ben) 00b t su(d-weh) t h(weh-d) d[15:0] 00b d[15:0] t w(we)
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 26 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller fig 19. 8-bit read a[7:1] cs re be0 to be1 d[15:0] t su(a) 002aad30 4 t su(a) t su(ben) t h(a) t h(re-cs) t d(re) t h(ben) 10b t d(re-q) t dis(re-qz) d[7:0] 01b d[15:8] t w(re) fig 20. 16-bit read a[7:1] cs re be0 to be1 d[15:0] t su(a) 002aad30 3 t su(a) t su(ben) t h(a) t h(re-cs) t d(re) t h(ben) 00b t d(re-q) t dis(re-qz) d[15:0] 00b d[15:0] t w(re)
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 27 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller fig 21. 25 mhz sdclk fig 22. 55 mhz sdclk 002aad30 6 t wl 0.2v dd sdclk t w(clk) t wh valid 0.7v dd t thl valid t tlh dat[7:0], cmd (input) dat[7:0], cmd (output) t isu t ih t odly(max) t odly(min) 0.7v dd 0.2v dd 002aad30 5 t wl 0.2v dd sdclk t w(clk) t wh valid 0.7v dd t thl valid t tlh dat[7:0], cmd (input) dat[7:0], cmd (output) t isu t ih t odly 50 % v dd t oh 0.7v dd 0.2v dd
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 28 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller fig 23. dma write fig 24. dma read t su(a8) 002aad32 4 a8 a[7:1] don't care dreq cs we sdclk t su(a8-cs) 12 n dma burst size 12 t d(sdclk-dreqh) n dma inter delay t d(csh-dreql)w t su(a8) 002aad32 5 a8 a[7:1] don't care dreq cs re sdclk t su(a8-cs) 12 n dma burst size 12 t d(sdclk-dreqh) n dma inter delay t d(csh-dreql)r
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 29 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller fig 25. buffer read ready interrupt fig 26. buffer write ready interrupt register 0x30 int we t d(buf_full-intl) 002aad52 1 t d(int_clr-inth) buffer read ready write to interrupt status register to clear register 0x30 int we t d(buf_emp-intl) 002aad52 2 t d(int_clr-inth) buffer write ready write to interrupt status register to clear fig 27. external clock timing external clock 002aad67 7 t x1_clk t wl(x1_clk) t wh(x1_clk) f x1 _ clk 1 t x1 _ clk --------------------- =
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 30 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 13. package outline fig 28. package outline sot969-1 (tfbga64); see table 1 , table note [1] references outline version european projection issue date iec jedec jeita sot969-1 - - - - - - - - - sot969- 1 06-09-22 06-09-27 unit a max mm 1.1 0.25 0.15 0.85 0.75 4.1 3.9 4.1 3.9 0.4 2.8 0.15 0.05 0.1 a 1 dimensions (mm are the original dimensions) t fbga64: plastic thin fine-pitch ball grid array package; 64 balls; body 4 x 4 x 0.8 mm 0 2.5 5 mm scale a 2 b 0.3 0.2 d e e e 1 e 2 2.8 v w y 0.08 y 1 b a ball a1 index area d e e 2 e 1/2 e b e 1 e 1/2 e a c b ? v m c ? w m a b c d e f h g 2468 1357 ball a1 index area c y c y 1 x detail x a a 1 a 2
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 31 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller fig 29. package outline sot1133-1 (hxqfn60u) references outline version european projection issue date iec jedec jeita sot1133-1 - - - - - - - - - sot1133-1_po 08-12-17 09-01-22 unit mm max nom min 0.50 0.48 0.46 0.05 0.02 0.00 5.1 5.0 4.9 2.90 2.85 2.80 5.1 5.0 4.9 2.90 2.85 2.80 2 3.5 3.5 0.10 0.07 0.05 0.07 a dimensions h xqfn60u: plastic thermal enhanced extremely thin quad flat package; no leads; 6 0 terminals; utlp based; body 5 x 5 x 0.5 mm sot1133- 1 a 1 b 0.35 0.30 0.25 dd h ee h 0.08 0.1 yy 1 e 0.5 e 1 e 2 e 3 2 e 4 er 0.5 k 0.25 0.20 0.15 l 0.35 0.30 0.25 l 1 0.35 0.30 0.25 lc v 0.05 w 0 2.5 5 mm scale terminal 1 index area b a d e c y c y 1 x detail x a a 1 terminal 1 index area e 2 e 1 e r e 4 e 3 e e 1/2 e 1/2 e a c b v c w b a c b v c w d h lc lc k l e h l 1 b1 a1 b5 d5 d8 d6 d7 d1 d4 d2 d3 a32 b20 b16 a25 a24 a17 b11 b15 a9 a8 b6 b10 a16
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 32 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 33 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 14.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 30 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 0 and 21 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 30 . table 20. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 21. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 34 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 30. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 35 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 15. appendix 15.1 errata added 2010-01-07 this errata describes the functional behavio r deviation of the sdio101 from the data sheet rev. 01. 15.1.1 card detection in hibernate mode or coma mode card detection does not work when the device is in coma mode or hibernate mode. when put in these modes, the sdio101 sd supply is powered down. when a card is inserted, the card detection circuit won't be able to detect the card because there is no power. workaround: if the card is to be put in hibernate mode or coma mode, a processor?s gpio pin with a pull-up resistor can be used to do card detect function. the pin is to be programmed as input, and set to interrupt on both edges. when a card is inserted, this gpio pin will be pulled low by the card and an interrupt is generate d. when a card is removed, this gpio pin will be pulled high by the pull-up resistor and an interrupt is generated. 15.1.2 16-bit host interface synchronization due to a design synchronization requirement between the host and the sdio, an external crystal cannot be used as a clock source for the sdio101. random interrupt lockups sometimes occur during data read and write to the sdio101 internal buffers when an external crystal is used between x1_clk and x2_clk pins. workaround: a workaround solution is to use one of the processor?s clocks as the input clock for the sdio101 (see data sheet section 6.4.3.1 for more detail). 15.1.3 sd side data rate limitation at 1.8 v the current device does not work at 52 mhz when the v dd(sd) supply is at 1.8 v. when powered at 1.8 v, the sd side works up to about 30 mhz. (please note that when v dd(sd) is 2.5 v to 3.3 v, there is no data rate lim itation and the device works up to 52 mhz). workaround: there is no known workaround solution for this issue, if the card is to be used at 52 mhz with 1.8 v supply. to run the card at 52 mhz, v dd(sd) must be powered at 2.5 v minimum. 15.1.4 high current on v dd pin after power-up after power-up, v dd pin draws close to 2 ma then the current slowly drops down to the idle current state at 68 a in about 40 seconds. this issue does not have any effect on the normal operation of the device, and the high current only occurs just after the device is powered up. workaround: we are investigating this issue to find out what might cause this problem. and, since the issue does not alter the behav ior of the device and a root cause has not been identified, there is not a workar ound for this issue at this time.
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 36 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 16. abbreviations 17. references [1] sd specifications part a2, sd host controller standard specification, version 2.00 , february 2007 [2] sd specifications part e1, sd io specification, version 2.00 , february 8, 2007 [3] sd specifications part 1, physical layer specification, version 2.0 , may 9, 2006 [4] the multimedia card, system specification version 4.1 [5] ce-ata digital protocol, version 1.1 18. revision history table 22. abbreviations acronym description ce-ata consumer electronics advanced technology attachment cpu central processing unit dma direct memory access fifo first in, first out gpio general purpose input/output io input/output kb kilobyte led light emitting diode mmc multi-media card pll phase-locked loop pu pull-up sd secure digital sdio secure digital input/output table 23. revision history document id release date data sheet status change notice supersedes sdio101_3 20100311 product data sheet - sdio101_2 modifications: ? table 1 ? ordering information ? : ? removed type number sdio101ihe (huqfn60u, sot1008-1). ? added type number sdio101ihr (hxqfn60u, sot1133-1). ? figure 4 ? pin configuration for hxqfn60u ? replaces (old) ?pin configuration for huqfn60u?. ? figure 5 ? terminal mapping for hxqfn60u ? replaces (old) ?terminal mapping for huqfn60u?. ? table 2 ? pin description by function ? : 3 rd column?s heading changed from ?huqfn60u? to ?hxqfn60u?. ? figure 29 ? package outline sot1133-1 (hxqfn60u) ? replaces (old) ?package outline sot1008-1 (huqfn60u)?. sdio101_2 20100119 product data sheet - sdio101_1 modifications: ? added errata section 15 ? appendix ? . sdio101_1 20090924 product data sheet - -
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 37 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 19.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 19.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicond uctors product is au tomotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive sp ecifications and standards, customer (a) shall use the product without nx p semiconductors? warranty of the document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
sdio101_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 11 march 2010 38 of 39 nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. 19.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors sdio101 sd/sdio/mmc/ce-ata host controller ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 11 march 2010 document identifier: sdio101_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 host processor interface. . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.2.1 pin description by function . . . . . . . . . . . . . . . . 7 6 functional description . . . . . . . . . . . . . . . . . . . 9 6.1 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.1 dma read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.2 dma write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2 standard host register overview. . . . . . . . . . . 10 6.3 standard host register set description . . . . . . 11 6.3.1 system address register (offset 0x00) . . . . . . 11 6.3.2 block size register (offset 0x04) . . . . . . . . . . . 11 6.3.3 transfer mode register (o ffset 0x0c) . . . . . . . 11 6.3.4 present state register (o ffset 0x24) . . . . . . . . 11 6.3.5 host control register (off set 0x28) . . . . . . . . . 11 6.3.6 power control register (o ffset 0x29) . . . . . . . . 11 6.3.7 capabilities register (offset 0x40) . . . . . . . . . . 12 6.4 additional register set description. . . . . . . . . . 12 6.4.1 io configuration register (offset 0x50) . . . . . . 12 6.4.2 dma register (offset 0xf4) . . . . . . . . . . . . . . . 13 6.4.3 secondary clock control register (offset 0xf6) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4.3.1 sdio101 x1_clk input . . . . . . . . . . . . . . . . . 15 6.4.4 miscellaneous register (offset 0xf8). . . . . . . . 16 6.4.5 pll register (offset 0xfa) . . . . . . . . . . . . . . . . 17 6.4.6 host controller version register (offset 0xfe) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 power-saving modes . . . . . . . . . . . . . . . . . . . 19 7 application design-in information . . . . . . . . . 19 8 basic architecture . . . . . . . . . . . . . . . . . . . . . . 20 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 21 10 recommended operating conditions. . . . . . . 21 11 static characteristics. . . . . . . . . . . . . . . . . . . . 22 12 dynamic characteristics . . . . . . . . . . . . . . . . . 23 12.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 25 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 14 soldering of smd packages . . . . . . . . . . . . . . 32 14.1 introduction to soldering . . . . . . . . . . . . . . . . . 32 14.2 wave and reflow soldering . . . . . . . . . . . . . . . 32 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 32 14.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 33 15 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 15.1 errata added 2010-01-07. . . . . . . . . . . . . . . . 35 15.1.1 card detection in hibernate mode or coma mode . . . . . . . . . . . . . . . . . . . . . . . . . . 35 15.1.2 16-bit host interface syn chronization . . . . . . . 35 15.1.3 sd side data rate limitation at 1.8 v. . . . . . . . 35 15.1.4 high current on v dd pin after power-up . . . . . 35 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 36 17 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 18 revision history . . . . . . . . . . . . . . . . . . . . . . . 36 19 legal information . . . . . . . . . . . . . . . . . . . . . . 37 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 37 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 37 19.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38 20 contact information . . . . . . . . . . . . . . . . . . . . 38 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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